The present disclosure relates to integrated circuit (IC) structures, and more specifically, to IC structures which include a cross-couple structure between vertical transistors.
With increasing miniaturization of electronics, vertically oriented transistors, also known as vertical field effect transistors (VFETs), are increasingly incorporated into devices such as random access memory (RAM) bitcell arrays, logic devices, etc. Manufacturing processes to form active elements in IC fabrication, e.g., RAM bitcell formation, may include forming a cross-coupling structure between the gate node of one transistor and the source/drain region of another transistor. RAM in particular may take the form of “static RAM” (SRAM) or “dynamic RAM” (DRAM). Processes to form the conductive coupling between these nodes typically require multiple additional masks to form and pattern the regions where conductive material will be formed on the gates and source/drain regions of paired transistors. The continued miniaturization of electronics and evolution of device architecture (e.g., incorporation of VFETs) accompanies a technical demand to reduce the surface area occupied by each circuit feature, e.g., cross-coupling regions, as well as the manufacturability of such features.
Several transistors can be electrically connected to each other to provide fundamental elements of a digital circuit's architecture. An SRAM cell typically includes six transistors, four of which can be wired to form two cross-coupled voltage inverters, each including a pair of transistors, for storing binary digits (also known as “bits”) in the form of “high” and “low” voltages, i.e., voltages above or below a predetermined threshold. The remaining two transistors in an SRAM structure can be known as “access transistors,” so named because these transistors can control electrical access to the SRAM cell during read and write operations. Reducing the size of memory components in an IC, including SRAM cells, can allow more bits to be stored on one product and thereby reduce manufacturing costs per bit of storage. The development of different transistor structures, e.g., VFETs, may permit re-examination or re-design of RAM architectures and/or other device architectures.